pp4fpgas
  • Parallel Programming for FPGAs: Projects and Labs
  • Project: FIR Filter Design
  • Project: CORDIC
  • Project: Phase Detector
  • Project: Discrete Fourier Transform (DFT)
  • Project: Fast Fourier Transform (FFT)
  • Project: OFDM Receiver
  • Project: AMD AI-Engine (AIE) Accelerator
  • Project: Matrix Multiplication on Intel DevCloud Using DPC++
  • Project: FM Demodulator
  • Project: Binary Neural Network (BNN)
  • Lab: Pynq Memory Mapped IO (s_axilite)
  • Using Vitis Unified IDE for HLS
  • Lab (Legacy): Pynq Memory Mapped IO (s_axilite)
  • Lab: Axistream Single DMA (axis)
  • Lab: Axistream Multiple DMAs (axis)
  • Lab: AXI4-Burst Mode (m_axi)
  • Lab: Interrupts
  • Lab: MicroBlaze
  • Lab: SYCL on Intel DevCloud
pp4fpgas
  • Search


© Copyright 2019, Sivasankar Palaniappan.

Built with Sphinx using a theme provided by Read the Docs.